The present invention relates to an elastic memory, and more particularly to an arrangement for reducing phase fluctuations in the output clock pulses of elastic memories as they occur upon the temporary absence and the reappearance of the external input clock pulse.
Elastic memories are used in data transmission for the insertion of additional data (stuffing process), for the extraction of additional data (unstuffing process) or to convert a noncontinuous data flow into a data flow having a clock pulse frequency equal to the average clock pulse frequency of the noncontinuous data flow (dejittering).
An elastic memory can be realized in various ways, with one such way being e.g., with the aid of shift registers. (CCITT Org. Book Vol III-2 Section 7, 1977. Weiss, Digitaler Multiplexer zweiter Ordnung DMX-8 von 8448 kBit/s mit positiver Stopftechnik, Hasler Mitteilungen Nr. 1 1978 TCM 2401, preliminary data sheet, Texas Instruments, 1980)
FIGS. 1 and 2 show conventional input and output signals for an elastic memory, which signals are substantially independent of the internal structure of the elastic memory. As shown in FIGS. 1 and 2, the elastic memory 1, has a first input 2 for the clock pulses for writing in the data (writing or input clock pulse), a second input 3 for the data to be written in, and a third input 4 for the clock pulses for reading out the data (reading or output clock pulse). The elastic memory 1 is also provided with a first output 5 for the data read out, and a further output 6 for the control signal. The control signal at output 6 contains the information about the distance between the cell i in which data has just been written and the cell i+m from which data has just read out for an elastic memory 1 comprising a total of n cells. The distance or number of cells m between the just written-in cell i and the just read-out cell i+m bears the reference numeral 7, the written-in cell i has the reference numeral 8, and read-out cell i+m has the reference numeral 9. Finally, a voltage controlled oscillator 14 is provided between the control signal output 6 and the reading clock pulse input 4.
The reading clock pulses at input 4 advance the reading process clockwise from cell to cell away from the current cell 9 and the writing clock pulses at input 2 advance the writing process clockwise from cell to cell away from the current cell 8. The control signal at output 6 is used to control the reading clock pulse during a stuffing process and to control the reading clock pulse during a dejittering process in such a way that the distance 7 between the written-in and read-out cells does not fall below a certain minimum value and the average frequency of the reading clock pulses is equal to the average frequency of the writing clock pulses.
Usually, a voltage controlled oscillator VCO 14, operating at a frequency which is regulated in the described manner by the regulating signal at output 6, is used as the controllable reading clock pulse generator.
This arrangement encounters problems if an external input clock pulse signal is missing. Then either the writing clock pulses or the reading clock pulses or both clock pulses are omitted. In this case, a useful control signal at output 6 is no longer available. That means, that the distance 7 can take on any desired value between 0 and n. If now the external input clock pulses are switched in again, the full operation of the circuit is realized only after a long, complicated regulating process until the distance 7 of at least m cells has been re-established.
These problems are nowadays usually solved in that, if a clock pulse signal is missing, the control signal at output 6 is replaced by a desired value, and the renewed inclusion of the clock pulse signal is delayed until the distance between the read-out and the written-in cell is greater than the required minimum distance. The control of these processes requires additional, complicated logic elements.